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Keep a folded int8 dtype through every retrace (#24239) - #24239
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Summary: Once Q/DQ is folded, the LUT activations (`tanh`, `sigmoid`, `silu`, `gelu`, `log*`, `sqrt`, `rsqrt`) and `div` take int8, but their ATen fake kernels promote it to float. Every pass retraces the graph, so each retrace labels these ops, and every view, permute, clamp and layout copy behind them. The dtype-based checks downstream then decline tensors that are int8 on device: e.g., `ValidateCortexMExplicitLayoutPass` rejects a convolution behind `tanh`. Fix the dtype during tracing, as the Arm backend does for ops whose fake kernel cannot handle quantized inputs. For these ops, when a node carries output qparams, the retrace takes its output dtype from them instead of from the fake kernel. Every pass that rebuilds the graph recomputes these types, and most passes in the Cortex-M lists are shared passes that don't know about this fix. So CortexMPassManager attaches it to every pass it runs. The one exception is AtenToCortexMPass, which replaces these ops with Cortex-M kernels that already report int8. The ops stay ATen until `AtenToCortexMPass`, and permute and layout-copy substitution still reads only the fake-tensor dtype, so an int8 graph that was never quantized lowers too. Authored with an AI coding assistant (Claude). Differential Revision: D128001102
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Summary: Once Q/DQ is folded, the LUT activations (`tanh`, `sigmoid`, `silu`, `gelu`, `log*`, `sqrt`, `rsqrt`) and `div` take int8, but their ATen fake kernels promote it to float. Every pass retraces the graph, so each retrace labels these ops, and every view, permute, clamp and layout copy behind them. The dtype-based checks downstream then decline tensors that are int8 on device: e.g., `ValidateCortexMExplicitLayoutPass` rejects a convolution behind `tanh`. Fix the dtype during tracing, as the Arm backend does for ops whose fake kernel cannot handle quantized inputs. For these ops, when a node carries output qparams, the retrace takes its output dtype from them instead of from the fake kernel. Every pass that rebuilds the graph recomputes these types, and most passes in the Cortex-M lists are shared passes that don't know about this fix. So CortexMPassManager attaches it to every pass it runs. The one exception is AtenToCortexMPass, which replaces these ops with Cortex-M kernels that already report int8. The ops stay ATen until `AtenToCortexMPass`, and permute and layout-copy substitution still reads only the fake-tensor dtype, so an int8 graph that was never quantized lowers too. Authored with an AI coding assistant (Claude). Differential Revision: D128001102
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Summary: Once Q/DQ is folded, the LUT activations (`tanh`, `sigmoid`, `silu`, `gelu`, `log*`, `sqrt`, `rsqrt`) and `div` take int8, but their ATen fake kernels promote it to float. Every pass retraces the graph, so each retrace labels these ops, and every view, permute, clamp and layout copy behind them. The dtype-based checks downstream then decline tensors that are int8 on device: e.g., `ValidateCortexMExplicitLayoutPass` rejects a convolution behind `tanh`. Fix the dtype during tracing, as the Arm backend does for ops whose fake kernel cannot handle quantized inputs. For these ops, when a node carries output qparams, the retrace takes its output dtype from them instead of from the fake kernel. Every pass that rebuilds the graph recomputes these types, and most passes in the Cortex-M lists are shared passes that don't know about this fix. So CortexMPassManager attaches it to every pass it runs. The one exception is AtenToCortexMPass, which replaces these ops with Cortex-M kernels that already report int8. The ops stay ATen until `AtenToCortexMPass`, and permute and layout-copy substitution still reads only the fake-tensor dtype, so an int8 graph that was never quantized lowers too. Authored with an AI coding assistant (Claude). Differential Revision: D128001102
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Summary: Once Q/DQ is folded, the LUT activations (`tanh`, `sigmoid`, `silu`, `gelu`, `log*`, `sqrt`, `rsqrt`) and `div` take int8, but their ATen fake kernels promote it to float. Every pass retraces the graph, so each retrace labels these ops, and every view, permute, clamp and layout copy behind them. The dtype-based checks downstream then decline tensors that are int8 on device: e.g., `ValidateCortexMExplicitLayoutPass` rejects a convolution behind `tanh`. Fix the dtype during tracing, as the Arm backend does for ops whose fake kernel cannot handle quantized inputs. For these ops, when a node carries output qparams, the retrace takes its output dtype from them instead of from the fake kernel. Every pass that rebuilds the graph recomputes these types, and most passes in the Cortex-M lists are shared passes that don't know about this fix. So CortexMPassManager attaches it to every pass it runs. The one exception is AtenToCortexMPass, which replaces these ops with Cortex-M kernels that already report int8. The ops stay ATen until `AtenToCortexMPass`, and permute and layout-copy substitution still reads only the fake-tensor dtype, so an int8 graph that was never quantized lowers too. Authored with an AI coding assistant (Claude). Differential Revision: D128001102
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Summary: Once Q/DQ is folded, the LUT activations (`tanh`, `sigmoid`, `silu`, `gelu`, `log*`, `sqrt`, `rsqrt`) and `div` take int8, but their ATen fake kernels promote it to float. Every pass retraces the graph, so each retrace labels these ops, and every view, permute, clamp and layout copy behind them. The dtype-based checks downstream then decline tensors that are int8 on device: e.g., `ValidateCortexMExplicitLayoutPass` rejects a convolution behind `tanh`. Fix the dtype during tracing, as the Arm backend does for ops whose fake kernel cannot handle quantized inputs. For these ops, when a node carries output qparams, the retrace takes its output dtype from them instead of from the fake kernel. Every pass that rebuilds the graph recomputes these types, and most passes in the Cortex-M lists are shared passes that don't know about this fix. So CortexMPassManager attaches it to every pass it runs. The one exception is AtenToCortexMPass, which replaces these ops with Cortex-M kernels that already report int8. The ops stay ATen until `AtenToCortexMPass`, and permute and layout-copy substitution still reads only the fake-tensor dtype, so an int8 graph that was never quantized lowers too. Authored with an AI coding assistant (Claude). Differential Revision: D128001102
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Summary: Once Q/DQ is folded, the LUT activations (`tanh`, `sigmoid`, `silu`, `gelu`, `log*`, `sqrt`, `rsqrt`) and `div` take int8, but their ATen fake kernels promote it to float. Every pass retraces the graph, so each retrace labels these ops, and every view, permute, clamp and layout copy behind them. The dtype-based checks downstream then decline tensors that are int8 on device: e.g., `ValidateCortexMExplicitLayoutPass` rejects a convolution behind `tanh`. Fix the dtype during tracing, as the Arm backend does for ops whose fake kernel cannot handle quantized inputs. For these ops, when a node carries output qparams, the retrace takes its output dtype from them instead of from the fake kernel. Every pass that rebuilds the graph recomputes these types, and most passes in the Cortex-M lists are shared passes that don't know about this fix. So CortexMPassManager attaches it to every pass it runs. The one exception is AtenToCortexMPass, which replaces these ops with Cortex-M kernels that already report int8. The ops stay ATen until `AtenToCortexMPass`, and permute and layout-copy substitution still reads only the fake-tensor dtype, so an int8 graph that was never quantized lowers too. Authored with an AI coding assistant (Claude). Differential Revision: D128001102
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Summary: Once Q/DQ is folded, the LUT activations (`tanh`, `sigmoid`, `silu`, `gelu`, `log*`, `sqrt`, `rsqrt`) and `div` take int8, but their ATen fake kernels promote it to float. Every pass retraces the graph, so each retrace labels these ops, and every view, permute, clamp and layout copy behind them. The dtype-based checks downstream then decline tensors that are int8 on device: e.g., `ValidateCortexMExplicitLayoutPass` rejects a convolution behind `tanh`. Fix the dtype during tracing, as the Arm backend does for ops whose fake kernel cannot handle quantized inputs. For these ops, when a node carries output qparams, the retrace takes its output dtype from them instead of from the fake kernel. Every pass that rebuilds the graph recomputes these types, and most passes in the Cortex-M lists are shared passes that don't know about this fix. So CortexMPassManager attaches it to every pass it runs. The one exception is AtenToCortexMPass, which replaces these ops with Cortex-M kernels that already report int8. The ops stay ATen until `AtenToCortexMPass`, and permute and layout-copy substitution still reads only the fake-tensor dtype, so an int8 graph that was never quantized lowers too. Authored with an AI coding assistant (Claude). Differential Revision: D128001102
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Thanks, looks good to me when CI passes. Hopefully this can just be temporary and the Aten kernels can be fixed to remain in int8 at some point. |
Summary: Once Q/DQ is folded, the LUT activations (`tanh`, `sigmoid`, `silu`, `gelu`, `log*`, `sqrt`, `rsqrt`) and `div` take int8, but their ATen fake kernels promote it to float. Every pass retraces the graph, so each retrace labels these ops, and every view, permute, clamp and layout copy behind them. The dtype-based checks downstream then decline tensors that are int8 on device: e.g., `ValidateCortexMExplicitLayoutPass` rejects a convolution behind `tanh`. Fix the dtype during tracing, as the Arm backend does for ops whose fake kernel cannot handle quantized inputs. For these ops, when a node carries output qparams, the retrace takes its output dtype from them instead of from the fake kernel. Every pass that rebuilds the graph recomputes these types, and most passes in the Cortex-M lists are shared passes that don't know about this fix. So CortexMPassManager attaches it to every pass it runs. The one exception is AtenToCortexMPass, which replaces these ops with Cortex-M kernels that already report int8. The ops stay ATen until `AtenToCortexMPass`, and permute and layout-copy substitution still reads only the fake-tensor dtype, so an int8 graph that was never quantized lowers too. Authored with an AI coding assistant (Claude). Differential Revision: D128001102
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Summary: Once Q/DQ is folded, the LUT activations (`tanh`, `sigmoid`, `silu`, `gelu`, `log*`, `sqrt`, `rsqrt`) and `div` take int8, but their ATen fake kernels promote it to float. Every pass retraces the graph, so each retrace labels these ops, and every view, permute, clamp and layout copy behind them. The dtype-based checks downstream then decline tensors that are int8 on device: e.g., `ValidateCortexMExplicitLayoutPass` rejects a convolution behind `tanh`. Fix the dtype during tracing, as the Arm backend does for ops whose fake kernel cannot handle quantized inputs. For these ops, when a node carries output qparams, the retrace takes its output dtype from them instead of from the fake kernel. Every pass that rebuilds the graph recomputes these types, and most passes in the Cortex-M lists are shared passes that don't know about this fix. So CortexMPassManager attaches it to every pass it runs. The one exception is AtenToCortexMPass, which replaces these ops with Cortex-M kernels that already report int8. The ops stay ATen until `AtenToCortexMPass`, and permute and layout-copy substitution still reads only the fake-tensor dtype, so an int8 graph that was never quantized lowers too. Authored with an AI coding assistant (Claude). Differential Revision: D128001102
pssrawat
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Summary: Once Q/DQ is folded, the LUT activations (`tanh`, `sigmoid`, `silu`, `gelu`, `log*`, `sqrt`, `rsqrt`) and `div` take int8, but their ATen fake kernels promote it to float. Every pass retraces the graph, so each retrace labels these ops, and every view, permute, clamp and layout copy behind them. The dtype-based checks downstream then decline tensors that are int8 on device: e.g., `ValidateCortexMExplicitLayoutPass` rejects a convolution behind `tanh`. Fix the dtype during tracing, as the Arm backend does for ops whose fake kernel cannot handle quantized inputs. For these ops, when a node carries output qparams, the retrace takes its output dtype from them instead of from the fake kernel. Every pass that rebuilds the graph recomputes these types, and most passes in the Cortex-M lists are shared passes that don't know about this fix. So CortexMPassManager attaches it to every pass it runs. The one exception is AtenToCortexMPass, which replaces these ops with Cortex-M kernels that already report int8. The ops stay ATen until `AtenToCortexMPass`, and permute and layout-copy substitution still reads only the fake-tensor dtype, so an int8 graph that was never quantized lowers too. Authored with an AI coding assistant (Claude). Differential Revision: D128001102
pssrawat
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Oct 29, 2026
Summary: Once Q/DQ is folded, the LUT activations (`tanh`, `sigmoid`, `silu`, `gelu`, `log*`, `sqrt`, `rsqrt`) and `div` take int8, but their ATen fake kernels promote it to float. Every pass retraces the graph, so each retrace labels these ops, and every view, permute, clamp and layout copy behind them. The dtype-based checks downstream then decline tensors that are int8 on device: e.g., `ValidateCortexMExplicitLayoutPass` rejects a convolution behind `tanh`. Fix the dtype during tracing, as the Arm backend does for ops whose fake kernel cannot handle quantized inputs. For these ops, when a node carries output qparams, the retrace takes its output dtype from them instead of from the fake kernel. Every pass that rebuilds the graph recomputes these types, and most passes in the Cortex-M lists are shared passes that don't know about this fix. So CortexMPassManager attaches it to every pass it runs. The one exception is AtenToCortexMPass, which replaces these ops with Cortex-M kernels that already report int8. The ops stay ATen until `AtenToCortexMPass`, and permute and layout-copy substitution still reads only the fake-tensor dtype, so an int8 graph that was never quantized lowers too. Authored with an AI coding assistant (Claude). Differential Revision: D128001102
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Summary: Once Q/DQ is folded, the LUT activations (`tanh`, `sigmoid`, `silu`, `gelu`, `log*`, `sqrt`, `rsqrt`) and `div` take int8, but their ATen fake kernels promote it to float. Every pass retraces the graph, so each retrace labels these ops, and every view, permute, clamp and layout copy behind them. The dtype-based checks downstream then decline tensors that are int8 on device: e.g., `ValidateCortexMExplicitLayoutPass` rejects a convolution behind `tanh`. Fix the dtype during tracing, as the Arm backend does for ops whose fake kernel cannot handle quantized inputs. For these ops, when a node carries output qparams, the retrace takes its output dtype from them instead of from the fake kernel. Every pass that rebuilds the graph recomputes these types, and most passes in the Cortex-M lists are shared passes that don't know about this fix. So CortexMPassManager attaches it to every pass it runs. The one exception is AtenToCortexMPass, which replaces these ops with Cortex-M kernels that already report int8. The ops stay ATen until `AtenToCortexMPass`, and permute and layout-copy substitution still reads only the fake-tensor dtype, so an int8 graph that was never quantized lowers too. Authored with an AI coding assistant (Claude). Reviewed By: rascani Differential Revision: D128001102
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Summary:
Once Q/DQ is folded, the LUT activations (
tanh,sigmoid,silu,gelu,log*,sqrt,rsqrt) anddivtake int8, but their ATen fake kernels promote it to float. Every pass retraces the graph, so each retrace labels these ops, and every view, permute, clamp and layout copy behind them. The dtype-based checks downstream then decline tensors that are int8 on device: e.g.,ValidateCortexMExplicitLayoutPassrejects a convolution behindtanh.Fix the dtype during tracing, as the Arm backend does for ops whose fake kernel cannot handle quantized inputs. For these ops, when a node carries output qparams, the retrace takes its output dtype from them instead of from the fake kernel. Every pass that rebuilds the graph recomputes these types, and most passes in the Cortex-M lists are shared passes that don't know about this fix. So CortexMPassManager attaches it to every pass it runs. The one exception is AtenToCortexMPass, which replaces these ops with Cortex-M kernels that already report int8.
The ops stay ATen until
AtenToCortexMPass, and permute and layout-copy substitution still reads only the fake-tensor dtype, so an int8 graph that was never quantized lowers too.Authored with an AI coding assistant (Claude).
Differential Revision: D128001102